1. Technical Field
The embodiment described herein relates to a semiconductor apparatus, particularly an input buffer circuit.
2. Related Art
Conventionally, an input buffer, as shown in FIG. 1, includes a first buffering unit 10 and a second buffering unit 20.
The first buffering unit 10 generates first and second compare signals ‘com_s1’, ‘com_s2’ by comparing the levels of the voltage of an input signal ‘in’ and reference voltage ‘Vref’. For example, the first buffering unit 10 generates the first compare signal ‘com_s1’ at a lower voltage level than the voltage level of the second compare signal ‘com_s2’, when the voltage level of the input signal ‘in’ is higher than the level of the reference voltage ‘Vref’. Further, the first buffering unit 10 generates the first compare signal ‘com_s1’ at a higher voltage level than the voltage level of the second compare signal ‘com_s2’, when the voltage level of the input signal ‘in’ is lower than the level of the reference voltage ‘Vref’
The second buffering unit 20 generates an output signal ‘out’ by comparing the voltage levels of the first compare signal ‘com_s1’ and the second compare signal ‘com_s2’. For example, the second buffering unit 20 outputs the output signal ‘out’ at a low level, when the voltage level of the first compare signal ‘com_s1’ is higher than the voltage level of the second compare signal ‘com_s2’. Further, the second buffering unit 20 outputs the output signal ‘out’ at a high level, when the voltage level of the first compare signal ‘com_s1’ is lower than the voltage level of the second compare signal ‘com_s2’.
Conventional input buffer circuits having the above configuration are vulnerable to noise of the reference voltage ‘Vref’ which is inputted into the first buffering unit 10. For example, when the level of the reference voltage ‘Vref’ becomes higher than a target level, the voltage level of the second compare signal ‘com_s2’ decreases. As the voltage level of the second compare signal ‘com_s2’ decreases, the voltage level of the first compare signal ‘com_s1’ becomes higher than the voltage level of the second compare signal ‘com_s2’. As a result, a problem is generated in that the output signal ‘out’ should change the voltage level by the change of the voltage level of the input signal ‘in’, but the output signal ‘out’ is always fixed to a low level. On the other hand, the voltage level of the output signal ‘out’ can be fixed to a high level, when the level of the reference voltage ‘Vref’ becomes lower than the target level. That is, the first buffering unit 10 amplifies noise of the reference voltage ‘Vref’ and then the second buffering unit 20 compares the second compare signal ‘com_s2’ with the first compare signal ‘com_s1’, such that a problem of a fixed level of the output signal ‘out’ occurs.
An input buffer circuit shown in FIG. 2 is a conventional input buffer circuit designed not to be influenced by noise of reference voltage, which includes a first buffering unit 10-1 and a second buffering unit 20-1, as in FIG. 1.
The first buffering unit 10-1 generates a compare signal ‘com_s’ by comparing the voltage levels of reference voltage ‘Vref’ with the input signal ‘in’. For example, when the voltage level of the input signal ‘in’ is higher than the level of the reference voltage ‘Vref’, the first buffering unit 10-1 generates the compare signal ‘com_s’ at a lower level than when the voltage level of the input signal ‘in’ is lower than the level of the reference voltage ‘Vref’. Further, when the voltage level of the input signal ‘in’ is lower than the level of the reference voltage ‘Vref’, the first buffering unit 10-1 generates the compare signal ‘com_s’ at a higher level than when the voltage level of the input signal ‘in’ is higher than the level of the reference voltage ‘Vref’.
The second buffering unit 20-1 generates an output signal ‘out’ by comparing the voltage levels of the input signal ‘in’ and the compare signal ‘com_s’. For example, the second buffering unit 20-1 outputs the output signal ‘out’ at a high level, when the voltage level of the input signal ‘in’ is higher than the voltage level of the compare signal ‘com_s’. The second buffering unit 20-1 outputs the output signal ‘out’ at a low level, when the voltage level of the input signal ‘in’ is lower than the voltage level of the compare signal ‘com_s’.
The input buffer circuit of FIG. 2 having the above configuration is less sensitive to noise of the reference voltage ‘Vref’ than the input buffer circuit shown in FIG. 1. This is because, different from the first buffering unit 10 shown in FIG. 1, the first buffering unit 10-1 does not generate a second compare signal ‘com_s2’ that is influenced by the reference voltage ‘Vref’, and the second buffering unit 20-1 does not amplify noise of the reference voltage ‘Vref’, because it receives only the input signal ‘in’ and the compare signal ‘com_s’.
However, the input buffer circuit shown in FIG. 2 is vulnerable to changes in level of external voltage ‘VDD’. The voltage level of the compare signal ‘com_s’ outputted from the first buffering unit 10-1 is in inverse proportion to the level of bias voltage ‘Bias’. That is, the bias voltage ‘Bias’ is a voltage controlling the degree of turn-on of a transistor N7, and as the level of the bias voltage ‘Bias’ increases, the degree of turn-on of the transistor N7 increases, such that the voltage level of a node where a resistor R3 and a transistor N8 are coupled, that is, the voltage level of the compare signal ‘com_s’ decreases. The level of the bias voltage ‘Bias’ increases in proportion to the level of the external voltage ‘VDD’. As a result, as the level of the external voltage ‘VDD’ increases, the level of the bias voltage ‘Bias’ increases, and the voltage level of the compare signal ‘com_s’ decreases on account of the bias voltage ‘Bias’ with increased voltage level. Since the second buffering unit 20-1 determines the voltage level of the output signal ‘out’ by comparing the decreased voltage levels of the compare signal ‘com_s’ with the input signal ‘in’, the voltage level of the output signal ‘out’ can be fixed to a high level.